PluriBus UT1-2M

Utopia Level 1 & 2 MPHY Master Core

Features:

• UTOPIA Level 1/Level 2 Master.  In Level 2, all "multi PHY" modes are supported:

  • 1 RxClav/1 TxClav

  • Direct Status

  • Multiplexed Status Polling

• Single- and multi-PHY operation, scalable from 1 to 31 links

• Performs ATM cell mux/demux and UTOPIA bridge functions

• Per port individual FIFOs or multi-port FIFOs optimized for block RAMs.  Programmable FIFO size.

• Continuous round-robin polling of programmable range of UTOPIA addresses

• Automatic port selection based on cell available status and FIFO thresholds

• Intelligent SOC error recovery

• 8/16-bit bus width

• Parity generation/checking with programmable parity sense

• Programmable cell length

• Programmable HEC generation

• 25/33/50 MHz and higher operation

• Flexible control inputs with options for:

  • internal/external hardwiring

  • access via a parallel or serial microprocessor interface

• Fully automatic test bench including ATM Layer driver/monitor and UTOPIA driver/monitor.  

Test Bench Features:

• Self checking test bench

• Random data generation

Standards Compliance:

• ATM Forum UTOPIA Level 1 Version 2.1

• ATM Forum UTOPIA Level 2 Version 1.0

Additional Information:

• Data Sheet

• Deliverables

• Tools Supported

• Request Information

Description

The ATM UTOPIA Master Core from Modelware implements, in modular VHDL, the master functions of the ATM Forum's UTOPIA Level 1 and Level 2 specifications.

Figure 1: Utopia Master Core Application

The core interfaces to the ATM Layer via a generic FIFO interface, and to single or multiple Physical  Layer (MPHY) ports via a UTOPIA Level 1 or Level 2 interface (Figure 1).  The core monitors, in round-robin fashion, a programmable range of PHY ports and optionally reports their "cell available" status to the ATM Layer.  In automatic selection mode, the core selects a port when its cell available indication is active and the corresponding FIFO is ready to transfer data to/from that port.  In ATM-controlled selection mode, the core monitors, in round-robin fashion, a programmable range of PHY ports and reports their "cell available" status to the ATM Layer.  The ATM Layer issues commands to the UTOPIA Master core to select a PHY port and initiate a cell transfer.

Size Information