PluriBus SPI4.2 Manager

SPI-4 Phase 2 Manager Core

Features:

  • OIF-compliant SPI-4 Phase 2 (compatible with Saturn Group POS-PHY L4)
  • Fully synchronous design, exceeds: 1 Gb/s (500 MHz DDR)
  • Static and dynamic timing alignment
  • Training Sequence generation and detection
  • DIP-4 Parity generation and checking
  • Handles continuous back-to-back End Of Packets (EOP) (2N + 1-byte packets) with shared control words
  • 64-bit or 128-bit PluriBus user interface in each direction for easy integration with user’s logic
  • Out-of-band packet signaling with SOP, EOP, Mod, and Err on PluriBus User Interface.
  • Start Of Packet (SOP) data to MSB alignment function.
  • Single- and multi-link operation, scalable from 1 to 256 links.
  • Multi-channel FIFOs with programmable size per channel
  • Automatic sink flow control generation (RStat)
  • FIFO Status channel framing and DIP-2 generation/checking (TStat)
  • Per channel credit management, and source data scheduler
  • Normal and high-speed FIFO Status Channel (run-time selectable)
  • Hitless Bandwidth Provisioning
  • Packet segmentation and reassembly
  • SOP/EOP checking
  • ASIC and FPGA support

Test Bench Features:

Rx/Sink Direction:
  • Automatic SPI-4.2 Control word generation according to packet signaling in source data files
  • Programmable data rate per channel
  • Clock to data skew insertion and relative bit skewing in fractions of a bit time
  • Clock jitter insertion
  • Programmable data packing with idle control word insertion between bursts or shared control word generation
  • DIP-4 and DIP-2 error insertion

Tx/Source Direction:
  • Control word decoding
  • Per-channel Virtual FIFOs with programmable depth and thresholds to generate flow control to core
  • DIP-4 and DIP-2 checking

Standards Compliance:

  • OIF SPI-4 Phase 2

  • Saturn Group (PMC-Sierra) POS-PHY L4

Additional Information:

Description

Modelware’s SPI-4.2 Manager core builds on the SPI-4.2 Foundation core and implements per-channel buffering, scheduling, and flow control functions to provide the user with a complete SPI-4.2 Link Layer solution.  Both SPI-4.2 Foundation and Manager cores optionally include the SPI-4.2 PHY Layer including deskew.

The SPI-4.2 Foundation Sink section monitors the Rx Data and controls the Rx Status. The Rx Data logic performs the dynamic/static alignment, converts the data bus from 16-bit DDR data and 1-bit DDR control to 64-bit SDR data and 4-bit SDR control, and decodes SPI-4.2 control and data words. The Rx Status logic generates the status frames containing per-channel flow control information according to the programmed calendar.

The Packet Processor monitors the incoming packet stream and provides various error detection, prevention, and tagging mechanisms to ensure that only valid packets are written into the FIFO.

The Status Generator encodes the fill-level of the per-channel FIFOs into the SPI-4.2 three-state flow-control information (STARVING, HUNGRY, SATISFIED) based on the MaxBurst1, MaxBurst2 interface parameters.

The Sink multi-channel FIFO provides independent data storage for the active channels. The FIFO architecture implements efficient channel switching and packet SAR functions.

The SPI-4.2 Foundation Source section controls the Transmit Data channel and monitors the Transmit Status channel. The Transmit Data channel logic reads the data from the FIFO, generates the SPI-4.2 control and data word stream, and converts the data from 64-bit SDR data and 4-bit SDR control to 16-bit DDR data and 1-bit DDR control. The Transmit Status Channel logic receives the SPI-4.2 status frame, checks DIP-2 parity, and decodes the per-channel flow-control information.

The Source multi-channel FIFO implements independent data storage for the active channels and provides the user with a simple per-channel flow control indication.

The Credit Processor decodes the per-channel three-state SPI-4.2 flow control information (STARVING, HUNGRY, SATISFIED) based on the MaxBurst1, MaxBurst2 interface parameters and controls the amount and the rate of traffic sent to each of the active channels.

The Transmit Scheduler executes the channel scheduling and data transfer. The calendar-driven selection of the next channel is performed in parallel with the data transfer of the current channel to maximize bandwidth utilization.

Size Information

Configuration

 Logic

Memory

Manuf.

Family

 PHY Layer

 40K Gates 0 ASICs --
 Link Layer
 (16 channels)		 350K Gates 300 Kbits ASICs --
 PHY+Link
 (16 channels)		 19.2K LEs 72 M4Ks Altera Stratix I/II
 PHY+Link
 (16 channels)		 8.5K Slices 31 B-RAMs Xilinx V2Pro/V4

  Note: Logic and memory size are configuration dependent.

ASIC Technology

The SPI-4.2 Core, including the PHY Layer is a synthesizable soft core and is compatible with any ASIC technology.  The core has been successfully implemented in the following technologies:

  • IBM: 0.13

  • KLSI: 0.13

  • LSI Logic: 0.13 and 0.18

  • NEC: 0.13

  • TI: 0.13

  • TSMC: 0.13, 0.15, and 0.18

  • UMC: 0.13

 

The "Ready for IBM Technology" trademarks and the trademarks contained therein are owned by IBM Corp and used under license to indicate that Modelware has tested the PluriBus SPI-4.2 cores for compatibility with IBM ASIC Products.  IBM did not make and is not responsible for the PluriBus SPI-4.2 cores.

Interoperablity

The SPI-4.2 Core has successfully interoperated with devices from the following ASSP manufacturers:

  • AMCC

  • Dune Networks

  • Intel

  • Network Elements

  • PMC Sierra

  • Zettacom/IDT