PluriBus SPI4.2 Foundation

SPI-4 Phase 2 Foundation Core

Features:

  • OIF-compliant SPI-4 Phase 2 (compatible with Saturn Group POS-PHY L4)
  • Fully synchronous design, exceeds: 1 Gb/s (500 MHz DDR)
  • Static and dynamic timing alignment
  • Training Sequence generation and detection
  • DIP-4 Parity generation and checking
  • Handles continuous back-to-back End Of Packets (EOP) (2N + 1-byte packets) with shared control words
  • 64-bit or 128-bit PluriBus user interface in each direction for easy integration with user’s logic
  • Out-of-band packet signaling with SOP, EOP, Mod, and Err on user interface.
  • Start Of Packet (SOP) data to MSB alignment function.
  • Single- and multi-link operation, scalable from 1 to 256 links.
  • Single Sink and Source FIFOs for all channels
  • Programmable FIFO size
  • FIFO Status channel framing and DIP-2 generation/checking
  • Normal and high-speed FIFO Status Channel (run-time selectable)
  • Hitless Bandwidth Provisioning
  • ASIC and FPGA support

Test Bench Features:

Rx/Sink Direction:
  • Automatic SPI-4.2 Control word generation according to packet signaling in source data files.
  • Programmable data rate per channel
  • Clock to data skew insertion and relative bit skewing in fractions of a bit time
  • Clock jitter insertion
  • Programmable data packing with idle control word insertion between bursts or shared control word generation
  • DIP-4 and DIP-2 error insertion

Tx/Source Direction:
  • Control word decoding
  • Per-channel Virtual FIFOs with programmable depth and thresholds to generate flow control to core
  • DIP-4 and DIP-2 checking

Standards Compliance:

  • OIF SPI-4 Phase 2

  • Saturn Group (PMC-Sierra) POS-PHY L4

Additional Information:

Description

Modelware’s SPI-4.2 Foundation core implements the OIF SPI-4.2 standard including the Link Layer and the digital portion of the PHY Layer.

The SPI-4.2 Sink High-Speed section performs the dynamic alignment and converts the data bus from 16 bits of DDR Data + 1 bit of DDR control to 64-bit SDR data and 4-bit SDR control. The Sink High-Speed section is a fully synchronous digital circuit that interfaces to a third-party PLL.

The SPI-4.2 Sink section frames on the Receive Data channel by monitoring and checking DIP-4 parity codewords. The received data is stored in the Sink FIFO with out-of-band SOP, EOP, ERR, MOD, and ADDR information. By using an advanced architecture, the Sink/FIFO subsystem can receive and store successive back-to-back 1-word EOP’s for all active channels, and exceeds the OIF specification by accepting successive SOPs within 8 cycles.

The SPI-4.2 Receive Status channel outputs the per-channel flow control information from the user. The Sink block generates the FIFO Status Channel frame according to the programmed calendar and including the framing and DIP-2 parity.

The SPI-4.2 Source section frames on the Transmit Status channel by monitoring and checking DIP-2 parity codewords and decodes flow-control information according to the programmed calendar. The decoded per-channel flow-control information is sent to the user for processing.

In the Tx/Source direction the user writes the data with out-of-band SOP, EOP, ERR, MOD, and ADDR information into the Source FIFO. The core monitors the fill-level of the FIFO, reads out complete bursts of data, and generates SPI-4.2 control and data words on the SPI-4.2 Transmit Data channel. The Source always generates Training Patterns on start-up and can be programmed insert Training Sequence at certain intervals. If there is no user data in the Source FIFO, the SPI-4.2 Source section generates IDLE control words. The Source section calculates and inserts DIP-4 parity in every control word.

The SPI-4.2 Tx High-Speed section converts the 64-bit SDR data and 4-bit SDR control to 16-bit DDR data and 1-bit DDR control. Tx High-Speed section can be configured for either muxed or registered DDR.

Size Information

Configuration Logic

Memory

Manuf.

Family

 PHY Layer

 40K Gates 0 ASICs --
 Link Layer 50K Gates 70 Kbits ASICs --
 PHY+Link 8.3K LEs 17 M4Ks Altera Stratix I/II
 PHY+Link 3.7K Slices 17 B-RAMs Xilinx V2Pro/V4

  Note: Logic and memory size are configuration dependent.

ASIC Technology

The SPI-4.2 Core, including the PHY Layer is a synthesizable soft core and is compatible with any ASIC technology.  The core has been successfully implemented in the following technologies:

  • IBM: 0.13

  • KLSI: 0.13

  • LSI Logic: 0.13 and 0.18

  • NEC: 0.13

  • TI: 0.13

  • TSMC: 0.13, 0.15, and 0.18

  • UMC: 0.13

 

The "Ready for IBM Technology" trademarks and the trademarks contained therein are owned by IBM Corp and used under license to indicate that Modelware has tested the PluriBus SPI-4.2 cores for compatibility with IBM ASIC Products.  IBM did not make and is not responsible for the PluriBus SPI-4.2 cores.

Interoperablity

The SPI-4.2 Core has successfully interoperated with devices from the following ASSP manufacturers:

  • AMCC

  • Dune Networks

  • Intel

  • Network Elements

  • PMC Sierra

  • Zettacom/IDT