PluriBus SPI4.1

SPI-4 Phase 1 Core

Features:

• OIF-compliant SPI-4 Phase 1 (compatible with AMCC FlexBUS-4) with FIFOs
• ATM, Packet Over SONET (POS), and Direct Data Mapping modes. Direct Data Mapping is a raw data mode supported in AMCC’s Ganges device.
• Single- and multi-link operation, scalable from 1 to 16 links.
• Programmable per-port bandwidth allocation
• Programmable FIFO size with programmable almost empty/almost full thresholds.
• Programmable burst size
• Automatic link selection in the Source block based on Source FIFO threshold and flow control information.
• 64-bit data bus width.
• Parity generation/checking over data and control words
• Modelware's PluriBus Interface on user’s side. Altera's Atlantic interface also available.
• Full synchronous design, exceeds: Clk = 200 MHz
• Easy to use in Mux/Demux and bridge functions

Description

The Optical Interworking Forum’s (OIF) SPI-4 Phase 1 interface allows the interconnection of Physical Layer devices to Link Layer devices in 10Gb/s ATM, POS, and Ethernet applications.  Modelware’s SPI-4 Phase 1 core performs the interface functions on both sides of the interface as shown in Figure 1and Figure 2.

Figure 1: SPI-4 Phase 2 PHY Layer Application

Figure 2: SPI-4 Phase 2 Link Layer Application

On the system side, the SPI-4 Phase 1 core interfaces to a single or to multiple links or ports via Modelware's PluriBus interface.

The Spi4Tx block monitors the Source FIFOs fill level and the flow control information received from the opposite side of the SPI-4 interface.  If a Source FIFO has data and the flow control information for the corresponding channel indicates that it is ready to accept data, the Spi4Tx block initiates a data transfer from the Source FIFO towards the SPI-4 interface.

The Spi4Rx block transmits the Sink FIFO status information to the opposite side according to the Sink FIFO almost-full flags.  The Spi4Rx block stores data received for a particular link in that link’s FIFO.  Sink FIFO flags indicate to the user the presence of data in the FIFO(s).

Size Information

Please contact Modelware for ASIC sizes.