PluriBus PL3P Manager

POS-PHY Level 3 Physical Layer Manager Core

Features:

  • Standards-compliant POS-PHY Level 3/SPI-3 Physical Layer.

  • Single- and multi-PHY operation, scalable from 1 to 256 channels

  • Per-channel FIFOs with configurable size.

  • Automatic channel selection in the Rx direction based on Rx FIFO threshold and End Of Packet arrival

  • Automatic Tx flow control generation based on programmable FIFO fill level

  • Programmable burst length

  • Packet- and byte-level modes

  • Independently programmable high and low watermarks for packet available signal generation on PluriBus interface.

  • Parity generation/checking

  • SOP/EOP error checking

  • Supports transfer of ATM cells

  • 8-/16-/32-bit bus widths

  • Easy to use in Mux/Demux and bridge designs

  • Fully synchronous design, exceeds: FClk:104 MHz, Tco = 6ns, Tsu = 2ns, Th = 0.5ns.

  • ASIC and FPGA support

Test Bench Features:

  •  Fully automatic test bench

  • Sophisticated PL3 driver/monitor that emulates the Link Layer

  •  Programmable data rate per channel

  • Error insertion

Standards Compliance:

  • SATURN Group POS-PHY Level 3 Version 4.0

  • OIF SPI-3

Interoperability:

  • PMC Sierra

Additional Information:

Description

Modelware’s PluriBus POS-PHY L3 Physical Layer Core implements the Physical Layer functions of the SATURN Group's POS-PHY Level 3 specification.

The core interfaces to Physical Layer devices (e.g., Framers, HDLC, Ethernet MACs) via the easy-to-use PluriBus interface.  In the Rx direction, the core monitors the fill level of the Rx FIFOs.  When a FIFO reaches a programmable threshold or has an End of Packet, the core outputs the corresponding channel number followed by Rx data from that FIFO.  The burst length is programmable.  The Link Layer device can pause the core by negating the Rx enable signal.  In the Tx direction, the core monitors the Tx FIFOs and reports the packet available status in both byte and packet modes.  The Tx FIFO high and low watermarks can be programmed independently.  When the Link Layer device transmits data to a particular channel, the core decodes the in-band link number and writes the data to the corresponding FIFO.

Size and Performance Information

Configuration

Size

 Freq

Manuf.

Process

 16 Channels

7214 LE
20 M4K

 > 104 MHz Altera Stratix
 16 Channels 3538 Slices
6 RAMB16		 > 104 MHz Xilinx Virtex II

 16 Channels

 61K Gates
80K RAM Bits		 > 104 MHz TSMC 0.15µ

Please contact Modelware for other configurations.