PluriBus PL3L Manager

POS-PHY Level 3 Link Layer Manager Core

Features:

  • Standards-compliant POS-PHY Level 3/SPI-3 Link Layer.

  • Single- and multi-PHY operation, scalable from 1 to 256 channels

  • Per-channel FIFOs with configurable size.

  • Automatic Rx flow control based on Rx programmable FIFO fill level

  • Automatic channel selection in the Tx direction based on Tx FIFO threshold and End Of Packet arrival

  •  Programmable burst length

  •  Packet- and byte-level modes

  • Independently programmable high and low watermarks for packet available signal generation on PluriBus interface.

  • Parity generation/checking

  • SOP/EOP error checking

  • Supports transfer of ATM cells

  • 8-/16-/32-bit bus widths

  • Easy to use in Mux/Demux and bridge designs

  • Fully synchronous design, exceeds: FClk:104 MHz, Tco = 6ns, Tsu = 2ns, Th = 0.5ns.

  • ASIC and FPGA support

Test Bench Features:

  •  Fully automatic test bench

  • Sophisticated PL3 driver/monitor that emulates the PHY Layer

  •  Programmable data rate per channel

  • Error insertion

Standards Compliance:

  • SATURN Group POS-PHY Level 3 Version 4.0

  • OIF SPI-3

Interoperability:

  • PMC Sierra

Additional Information:

Description

Modelware’s PluriBus POS-PHY L3 Link Layer Core implements the Link Layer functions of the SATURN Group's POS-PHY Level 3 and the Optical Internetworking Forum’s (OIF) System Packet Interface 3 (SPI-3) specifications.

The core interfaces to the user’s circuitry via the easy-to-use PluriBus interface.  In the Rx direction, the core decodes the in-band channel number and directs the Rx data to the corresponding FIFO.  In addition, the core monitors the fill level of the Rx FIFOs and negates Rx enable if the programmable threshold is exceeded on any of the channels.  In the Tx direction, the core monitors the fill level of the Tx FIFOs.  When a FIFO reaches a programmable threshold, or has an End Of Packet, the core outputs the corresponding channel number followed by a burst of data from that FIFO.  The burst size is programmable.

Size and Performance Information

Configuration

Size

 Freq

Manuf.

Process

 16 Channels

7214 LE
20 M4K

 > 104 MHz Altera Stratix
 16 Channels 3538 Slices
6 RAMB16		 > 104 MHz Xilinx Virtex II

 16 Channels

 61K Gates
80K RAM Bits		 > 104 MHz TSMC 0.15µ

Please contact Modelware for other configurations.