Modelware

PluriBus CSIX.1

Common Switch Interface Level 1 Core

Features:

CSIX-L1 Common Switch Layer-1 Interface

Individual FIFOs for data and flow control C-frames.

Programmable FIFO sizes and thresholds (empty and full)

Modelware PluriBus User interface.

Generates Modulo (valid bytes in the last cycle) with EOF (End of Frame) and error indicator based on C-frame length.

Programmable 32 / 64/ 96/ 128-bit physical data bus sizes.

Programmable max payload transfer size up to 256 bytes for each data and flow control C-frames (except headers, vertical parity and the padding bits)

Programmable frame identification for mapping flow control or data frames into the FIFOs

Programmable priority scheduler to serve data and control frames within certain ratio.

Horizontal (Out of band) and Vertical (Inband) Parity generation/checking

Alarm generation for programmable number of continuous vertical and horizontal parity errors.

Alarm generation for unexpected short frame and unidentified frame errors.

Meets the CSIX I/O timing specification

Configuration control inputs and registered alarm and status outputs.

Test Bench Features:

CSIX Interface side:

Programmable transmit and receive data rates for each data and flow control frame virtual FIFO

Programmable scheduler for data and flow control frames

Programmable odd/even parity generation and checking for vertical and horizontal parity

Programmable Vertical and horizontal parity error insertion

Programmable idle frame identification

Programmable physical data bus sizes

Programmable idle, data and flow control identification

Frame identification , unexpected frame, vertical parity and horizontal parity error checking

Programmable threshold and depth for each virtual FIFO

PluriBus Interface side:

Programmable transmit and receive data rate, threshold, depth for each data and flow control frame virtual FIFOs
Programmable scheduler in both FIFO driver and monitor to serve data and flow control frames from / to virtual FIFOs
Programmable physical data bus sizes

Loopbacks:

CSIX-side loopback
PluriBus-side loopback

Standards Compliance:

Network Processing Forum (NPF) Common Switch Interface Spec. L-1

Additional Information:

Description

Modelware’s CSIX.1 core implements the Network Processing Forum’s Common Switch Interface Level-1 specification.

The CSIX.1 core provides data transfer operations between traffic managers and switch fabrics via defined C-frames from 2.5Gbps (OC-48) up to 32Gbps. The CSIX.1 core is divided into Source and Sink sections each of which consists of an interface controller with generic FIFOs. Data and control frames are handled separately, i.e. the user circuit provides or receives data and control C-frames to/from the FIFOs independently. The FIFOs’ data bus sizes follow the CSIX-L1 physical interface data bus size.

In the sink direction, C-frame synchronization is continuously monitored with the reception of every Start Of Frame (SOF). If the synchronization fails, a pause is initiated via the Ready bits across the CSIX-L1 interface. During normal operation, while data and control frames are forwarded to their destination FIFOs, parity checkers verify both horizontal and vertical parity. When the Sink FIFOs become almost full, the core applies backpressure via the Ready bits.

In the source direction, the CSIX.1 core sends idle frames as long as the Sink section is out of C-frame synchronization. In normal mode, data and control frames are read from separate dedicated source FIFOs via a priority scheduler and are sent to the common physical bus. The user can program the scheduler to adjust the relative priority between data and control frames. Horizontal and Vertical parity for each frame are generated separately and added to the C-frames. The Source section continuously monitors the Ready bits received over the CSIX-L1 interface as well as the fill level of the Source FIFOs.

Size Information

Configuration	Size	Manuf.	Technology
32-bit data bus	22 M4Ks 3518 LEs	Altera	Stratix GX
64-bit data bus	36 M4Ks 4730 LEs	Altera	Stratix GX
32-bit data bus	10 Block RAM 1958 Slices	Xilinx	Virtex II Pro
64-bit data bus	12 Block RAM 2628 Slices	Xilinx	Virtex II Pro
32-bit data bus	35K Gates	TSMC	0.15µ
64-bit data bus	42K Gates	TSMC	0.15µ