nAccess™ MTC

Multi-channel Transmission Convergence Core

Features:

  • Scalable design: supports 31 DS1 or E1 lines over individual TDM Highways, or a single high-speed TDM Bus

  • Shared architecture to minimize size

  • ATM Header Error Correction (HEC) byte generation/checking

  • HEC-based cell delineation

  • Cell header single error correction/ multiple error detection

  • Cell payload scrambling/descrambling

  • Direct cell mapping

  • Idle cell insertion/deletion

  • Out of Cell Delineation (OCD)/Loss of Cell Delineation (LCD) status

  • User-programmable cell filter

  • 25 MHz UTOPIA Level 2 with parity  generation and checking

  • Supports independent or common line clocks

  • Supports internal or external FIFOs.

  • Programmable microprocessor interface compatible with Intel and Motorola microprocessors.

  • Can be used in conjunction with Modelware's Multi-Channel TC Core for applications requiring a transmission convergence function.

Test Bench Features:

  • Fully automatic test bench

  • Includes processor Bus Interface Model to configure MTC core and monitor alarms.

Standards Compliance:

  • ANSI T1.646-1995: Broadband-ISDN Physical Layer Specification for User-Network Interface Including DS1/ATM

  • ATM Forum User-Network Interface (UNI) Version 3.1

  • ATM Forum UTOPIA Level 2, v1.0

  • ITU-T Recommendation I.432: B‑ISDN User-Network Interface - Physical Layer Specification

Additional Information:

Description

The Multi-channel Transmission Convergence Core from Modelware implements, in modular VHDL, the Broadband ISDN (B-ISDN) functions of the Transmission Convergence (TC) sublayer.

The core consists of a line interface section and separate from the receive and transmit sections. This enables the user to use one of the available line interfaces or to create a custom interface without affecting the operation of the core.

The line interface section connects to line framers on one side via individual TDM Highway interfaces or a single high-speed TDM bus. On the other side, the line interface section interfaces to the receive and transmit sections over a simple parallel interface.

The Rx Cell Delineator block implements the cell delineation state machine and generates the Loss of Cell Delineation and Out of Cell Delineation events.  The Rx Cell Processor block performs the header error correction and descrambles incoming data before writing it into the Rx FIFO. The Rx Cell Processor can be configured to filter idle and user defined cells.

The Tx Cell Processor block reads cells from the Tx FIFO, and performs the payload scrambling and HEC generation.  If no cells are available in the Tx FIFO, the Tx Cell Processor can be configured to insert idle cells.

The core interfaces to the ATM layer over a Utopia level 2 interface which reads/writes cells from/to the Rx and Tx FIFOs  respectively. The architecture of the MTC core allows the substitution of the Utopia Level 2 interface with other interfaces to support more than 31 lines.

Size Information

Configuration

Size

Freq.

Manuf.

 Family

8-channel

7134 LEs

29 ESBs

 25MHz

Altera

 Apex

8-channel

2350 Slices

3 Blk RAMs

 25MHz

Xilinx

 Virtex II

Please contact Modelware for ASIC sizes.