nAccess™ IMA

Inverse Multiplexing for ATM Core

Features:

Description

Modelware’s IMA core implements  the ATM Forum’s  Inverse Multiplexing for ATM specification versions 1.0 and 1.1. The core is modular and scalable to 32 links and 32 groups, each link can be assigned to any group or configured as pass through

IMA provides modular bandwidth, using existing physical links (e.g. DS1/E1, JT2, DS3/E3), to access ATM networks and to interconnect ATM network elements. IMA groups a number of physical links to form a logical link whose bandwidth is approximately the sum of the bandwidth of the individual links.

The IMA Core interfaces to the PHY Layer and the ATM Layer over 2 UTOPIA level 2 interfaces. Modelware's Multi-Channel Transmission Convergence core can be used if needed to implement the Interface Specific Transmission Convergence sub-layer defined by the ATM Forum.

The IMA core is divided into a Link and Group sections which are interconnected via an internal UTOPIA Level 2 interface on which the Link section is the Slave and the Group section the Master. The microprocessor interface provides access to the IMA Core’s internal registers.

The Link Processor is a hardware circuit inside the Link section that implements the receive and transmit Link State Machines and the IMA Frame Synchronization Mechanism, and processes the link related fields of ICP cells. In addition, the Link Processor provides an interface to the external Delay Compensation Buffer to enable the IMA core to absorb the required link differential delay.

The Group Processor is a hardware circuit inside the Group section that implements the Group State Machine, the Group Traffic State Machine, and processes the group related fields of ICP cells. In addition, the Group Processor implements the IMA Data Cell Rate as defined in the IMA specification, and inserts the stuff events as required.

Size Information

Please contact Modelware for ASIC sizes.