nAccess™ HDLC-4K Foundation

4096-channel HDLC Foundation Core

General Features:

  • Standards-compliant HDLC Controller core

  • 8-bit physical link interface designed for easy interfacing to off-the-shelf framers

  • Flexible system interface allows easy connection to:

  • Data FIFOs

  • DMA controllers

  • POS-PHY interface cores

  • Flexible control inputs with options for:

  • internal/external hardwiring

  • access via a generic microprocessor interface

  • ASIC and FPGA support

HDLC Features:

  • Flag detection and generation

  • Abort detection and insertion

  • Zero-bit stuffing and destuffing

  • Selectable transparent mode

  • Selectable frame filtering based on:

  • Programmable 8 or 16-bit address field

  • Programmable 8 or 16-bit control field

  • Programmable 8 or 16-bit protocol field

  • Selectable frame header insertion (up to 6 programmable octets)

  • Selectable 16-bit, 32-bit, or no CRC generation and monitoring

  • CRC error generation

  • Selectable, programmable minimum interframe spacing

  • Programmable interframe time fill

  • Supports shared flags

  • Supports statistics counters for:

  • Received frames

  • Received short frames

  • Received long frames

  • Received CRC errored frames

  • Received aborted frames

  • Transmitted frames

  • Transmitted frames aborted

Test Bench Features:

  • Fully automatic test bench

  • Programmable data rate

  • Error insertion and monitoring

Standards Compliance:

  • ISO/IEC 3309

  • ITU-T Recommendation Q.921 (LAPD)

  • ITU-T Recommendation X.25 (LAPB)

  • RFC1619 and RFC1662

Additional Information:

Description

Modelware's nAccess HDLC-4K Foundation Core implements the ISO HDLC protocol and is compliant with ITU's X.25 LAPB and ISDN LAPD protocols. A typical application of the HDLC-4K Foundation core is shown in the figure below.

In the receive direction, the HDLC-4K Foundation core searches for a flag in the incoming bit stream to determine the frame alignment. Once the frame alignment is found, the core continuously monitors for data frames. The core performs the 0-bit destuffing and discards (according to the configuration) received frames with address, control, and protocol fields not matching the configured values. The CRC of each frame is also monitored and frames with incorrect CRC are tagged as errored frames. The received data frames are sent to the user via the Rx System Interface.

In the transmit direction, the HDLC-4K Foundation core continuously transmits flags or idle pattern (according to the configuration). After receiving a transmit request from the user, the core formats the frame by appending the header information and CRC (according to the configuration). The core then performs the 0-bit stuffing, sends the frame over the serial interface, and resumes the transmission of flags or idle pattern.

The core monitors and reports received errored or aborted frames, and receive overrun and transmit underrun conditions to the user.

Size Information

Configuration

Size

Freq.

Manuf.

 Family

256-channel, CRC16

1827 LEs,

2 M512s

10 M4Ks

> 100 MHz

Altera

 Stratix

256-channel, CRC16

1327 Slices

9 Block RAMs

> 100 MHz

Xilinx

 Virtex II

4096-channel, CRC16

1908 LEs,

68 M4Ks

2 M-RAMs

> 100 MHz

Altera

 Stratix

4096-channel, CRC16

1362 Slices

45 Block RAMs

> 100 MHz

Xilinx

 Virtex II

Please contact Modelware for ASIC sizes.