Adaptation AAL2/CPS

ATM Adaptation Level 2 CPS SAR

Features:

• AAL2 Common Part Sublayer scalable to 16K channels/ connections

• Mux/Demux of CPS Packets

• CPS with CPS-INFO max length of 45 and 64 bytes

• Programmable VPI/VCI, CID, and UUI per segmentation session.

• Programmable cell rate per VC

• Supports insertion and extraction of Layer Management CPS-Packets.

• Automatically extracts Layer Management CPS-Packets based on CID.

• Error checking and reporting: STF parity, STF sequence number, CPS-Packet length, HEC, UUI, CID.

• Easy-to-use PluriBus user packet interface

• UTOPIA L2 ATM Layer (Master) or Physical Layer (Slave)

• Can be integrated with Modelware’s SSSAR and/or voice SSCS

• Can be integrated with Modelware’s AAL 5 SAR

• Statistics: Packets received and transmitted, cells received and transmitted, errors.

Test Bench Features:

• Fully automatic test bench

• Programmable data rate

• Error insertion and monitoring

Standards Compliance:

• ITU I.366.1, 1998, Segmentation and reassembly service specific convergence sublayer for the AAL type 2

• ITU I.366.2, 1998, AAL type 2 service specific convergence sublayer for trunking

• ATM Forum: AF-VTOA-0113.000, 1999, ATM Trunking using AAL2 for Narrowband Services

Description

Modelware’s AAL2/CPS core implements the AAL 2 Common Part Sublayer (CPS).  The AAL 2 CPS core can interface directly to the user’s application or can be integrated with Modelware’s SSSAR and/or Service Specific Convergence Sublayers (SSCS).

The AAL 2 CPS core interfaces to the user’s application through the easy-to-use PluriBus packet interface.  On the ATM side, the core interfaces to an ATM switch or physical layer device through a UTOPIA L2 bus.

 For segmentation, the user programs the ATM header for each connection.  As shown in Figure 1, the user (or SSCS/SSSAR) sends the CPS Packets through the PluriBus interface.  The core adds the appropriate ATM header and buffers the cells until they are complete or until the Combined Use timer expires.  Full or partial cells are then sent to the UTOPIA block at a programmable rate per connection.  Layer Management cells are formatted by the microprocessor and written in a buffer for transmission to the ATM network.

 For reassembly, when a cell arrives from the UTOPIA block, the VPI/VCI bits are extracted and the Start Field (STF) is checked for correct parity, sequence number, and offset range.  Subsequently, the core checks the length and HEC for each CPS packet and stores them in the reassembly buffer according to the connection ID.  CPS Packets are delivered to the user’s application or SSSAR/SSCS as they arrive.  Layer Management cells are extracted and sent to a buffer to be read by the microprocessor.  The reassembly buffer may be implemented in internal or external memory, depending on capacity requirements.

Size Information

Please contact Modelware for other configurations and target technologies.