Adaptation AAL1

ATM Adaptation Level 1 Core

Features:

  • Scalable design supports 1024 timeslots/ connections

  • SAR for Circuit Emulation DS1/E1/J2/ DS3/E3, Constant Bit Rate Video and Audio.

  • Structured (SDT) and Unstructured Data Transfer (UDT)

  • SRTS and Adaptive clock modes for UDT

  •  Programmable partial fill

  • Basic and signaling formats

  • Supports DBCES

  • Supports insertion and extraction of Layer Management CPS-Packets.

  • Interfaces to industry-standard DS1/E1/J2/DS3/E3 framers

  • Can be integrated with Modelware’s AAL5 for signaling

  • Statistics: Frames received and transmitted, cells received and transmitted, errors.

Test Bench Features:

  • Fully automatic test bench

  • Programmable data rate

  • Error insertion and monitoring

Standards Compliance:

  • ATM Forum: Circuit Emulation Service Interoperability Specification, Versions 2.0

  • ATM Forum: Voice and Telephony Over ATM – ATM Trunking using AAL1 for narrowband Services Version 1.0 

  • ATM Forum: Specifications of (DBCES) Dynamic Bandwidth Utilization – In 64KBPS, Time Slot Trunking over ATM using CES.

  • ITU – I.363.1 : B –ISDN Adaptation Layer specification: Type 1 AAL.

Additional Information:

Description

Modelware’s ATM Adaptation Layer type 1 (AAL 1) core implements the Segmentation and Reassembly (SAR) and the Convergence Sub layers (CSs) for Circuit Emulation DS1/E1/J2/DS3/E3, Constant Bit Rate Video and Audio as defined by the ATM Forum. The block diagram of the core is shown in the figure below.

The AAL 1 core interfaces to DS1/E1/J2/ DS3/E3 framers or voice/Video processors through one or more timeslot busses.  On the ATM side, the core interfaces to an ATM switch or physical layer device through a UTOPIA Slave bus.

In the segmentation direction (TDM to ATM), the user programs the setup parameters, the timeslots, and ATM header for each VPI/VCI in service (timeslot or group of timeslots).  The core formats the data according to the programmed SAR type and forms the SAR Protocol Data Units (PDU).  Finally, the appropriate ATM header is added and the cell is sent to the UTOPIA block.  Layer Management cells are formatted by the microprocessor and written in a buffer for transmission to the ATM network.

In the reassembly direction (ATM to TDM), the user programs the setup parameters and the timeslots for each VPI/VCI in service (destination timeslot or group of timeslots). When a cell arrives from the UTOPIA block, 10 bits are extracted from the ATM header to form the Connection ID(any 10 bits can be selected).  Then, for each Connection ID, the SAR processing is performed and the timeslots are stored in the reassembly buffer according to the destination timeslot and the amount of buffering required.  Layer Management cells are extracted and sent to a buffer to be read by the microprocessor.

The core monitors and reports received errored or aborted frames, and receive overrun and transmit underrun conditions to the user.

Size Information

Configuration

Size

Manuf.

 Family

84 T1/E1, 1024 Connections

6568 LEs 171 M4K

Altera

 Stratix

84 T1/E1, 1024 Connections

4138 slices 51 Blk RAMs

Xilinx

 Virtex II Pro

Please contact Modelware for other configurations and target technologies.