Modelware’s SPI-4.2-Universal SmartBridge provides bi-directional interface and protocol translation between a SPI-4.2 interface and up to four 2.5 Gb/s or lower-speed ATM or packet interfaces.  Each Universal interface is implemented as a size-efficient single logic block that can be programmed independently to operate as SPI-3, PL2, UTOPIA 3, UTOPIA 2, and their variations.  This SmartBridge product provides valuable flexibility for designers interfacing a network processor with a SPI-4.2 interface to one or more 2.5 Gb/s or lower-speed interfaces.  In addition, the Universal interface can be software-programmed to run in any mode, which enables system designers to implement multi-protocol functionality on a single interface.

Each of the Universal interfaces and the SPI-4.2 interface can support up to 16 channels such that each SPI-4.2 channel can be bridged to any channel on any Universal interface.

Each SPI-4.2 channel has a FIFO for each direction.  Data received from the Universal interface is stored in the assigned SPI-4.2 FIFO and then transmitted on the SPI-4.2 interface according to the SPI-4.2 calendar programming.  Likewise, data received from the SPI-4.2 interface is stored in the corresponding channel FIFO and transmitted on the assigned Universal interface and channel.  Burst sizes on the Universal and SPI-4.2 interfaces may be the same or different.

Flow control on the SPI-4.2 and the Universal interfaces is independent and decoupled.  The SmartBridge contains per-channel FIFOs that allow flow control to be terminated on one side of the bridge and regenerated on the other.

In the Universal-to-SPI-4.2 direction, the SmartBridge monitors and acts on the STARVING/ HUNGRY/ SATISFIED indications from the peer SPI-4.2 device.  The Universal interfaces respond to polling according to the FIFO fill levels when running in Physical Layer mode.  When in ATM/Link Layer mode, the Universal interfaces do not schedule transfers to channels whose FIFOs are above a programmable threshold.

In the SPI-4.2 to Universal direction, the SmartBridge generates the SPI-4.2 RSTAT information according to the fill level of the channel FIFOs.  In addition, if a channel FIFO contains a burst or an EOP, the SmartBridge will indicate a cell/packet available in response to polling in the Physical Layer mode or schedule a transfer in the Link/ATM Layer mode.

The SPI-4.2 – Universal SmartBridge architecture is modular and can easily be adapted for adding other proprietary interfaces or packet processing functions.