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TO ENABLE DEPLOYMENT OF TERABIT NETWORKS The cores' 10 Gigabit per second performance significantly boosts bandwidth of the internet backbone SAN JOSE, Calif., March 12, 2001—Xilinx, Inc. (NASDAQ: XLNX) announced today the immediate availability of the Real POS-PHY Level 4 (PL4) cores, increasing POS-PHY performance by over four times. Part of the Xilinx Platform FPGA initiative, the cores provide system architects with the capability to design next-generation PL4 based 10 Gigabit ATM, Packet-over-SONET and 10 Gigabit Ethernet solutions for the first time. The single and multi-channel cores are compatible with industry-leading application specific standard products (ASSPs) at OC-192 and 10 Gigabit per second data rates and are compatible with POS-PHY Level 4 interface specified by the SATURN® development group. “The use of POS-PHY Level 4 for Gigabit and 10 Gigabit Ethernet line termination in addition to the mapping of IP into SONET/SDH has proven critical for broadband systems architects facing increasing time to market pressures," said Steve Perna, vice president and general manager of PMC-Sierra’s Optical Networking Division. “The cores satisfy the explosive growth of Gigabit Ethernet, IP and optical Networking equipment requirements." “The availability of the POS PHY Level 4 cores marks the first in a series of ultra-fast system interfaces Xilinx is supporting through the SystemIO portion of the Platform FPGA initiative,” said Dennis Segers, senior vice president and general manager of the Advanced Product Group at Xilinx. "With ever increasing bandwidth requirements, these cores implemented in Virtex-II FPGAs enable data to travel faster than ever before across the internet backbone. For example, 74 minutes of music or 650 megabits of data can now be transferred in 0.5 seconds using these new technologies." As a principal member of the Optical Internetworking Forum (OIF), Xilinx has worked closely with leading networking system developers on many OIF System Packet Interface Level standards. For example, POS-PHY Level 4 is known as the OIF System Packet Interface Level 4 Phase 2 (OIF-SPI4-02.0) implementation agreement. SystemIO Interfaces
The Xilinx POS-PHY Level 4 cores are available for purchase as Xilinx LogiCORETM products and optimized for Virtex-II devices and design tools. Xilinx delivers these LogiCORE products using the Xilinx CORE Generator tool to smoothly integrate the cores into the Xilinx design flow. The cores were developed in cooperation with ModelWare, Inc. a developer of virtual components for telecommunications functions. License price and availability
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